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 Source-Level Debugging of VHDL Designs. Models, Methods and Tools
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Source-Level Debugging of VHDL Designs. Models, Methods and Tools

издательство Книга по Требованию Локальные и корпоративные сети
Cтраниц 140        мягкая обложка       
Аннотация:It takes 50 to 80 percent of the time used for verification depending on the level of automation of the verification tools. Debugging, which is the process of locating and correcting a fault, is not done solely by designers. As design density and complexity of digital systems increase, the costs due to design faults increase exponentially. Fault localization may significantly reduce design cycle time by reducing the overall debugging time. The verification engineers, the ones who write and run the verification tests, usually spend quite a lot of their own time analyzing the failure traces themselves. Therefore, detecting, localizing, and correcting faults are crucial issues in today`s fast-paced and fault-prone development process. Debugging is one of the most time consuming tasks in the effort to improve system quality. Even with a detailed failing run in hand, locating and correcting a fault is a bland and time-consuming chore. This book focuses on models, methods, and techniques for the design and development of debugging tools and specifically addresses verification engineers. Test case generation and verification tools detect faults and provide the user with a failing run.
Издательство: Книга по Требованию
Год:2008
Цена:
2384 руб
Нет в наличии
Поиск: Source-Level Debugging of VHDL Designs. Models, Methods and Tools
НОВЫЙ ГОД СИМВОЛ 2013 ГОДАУКРАШЕНИЯ
КАРНАВАЛ НА НОВЫЙ ГОД РАСПРОДАЖА
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